1. Field of the Invention
The present invention relates to a shift register, and more particularly, to a shift register capable of pre-charging to extend a time period of charging pixels.
2. Description of the Related Art
With a rapid development of monitor types, novel and colorful monitors with high resolution, e.g., liquid crystal displays (LCDs), are indispensable components used in various electronic products such as monitors for notebook computers, personal digital assistants (PDAs), digital cameras, and projectors. The demand for the novelty and colorful monitors has increased tremendously. A Low Temperature Poly-Silicon Liquid Crystal Display (LTPS LCD) panel, on account of high resolution demands, is widely applied to various electronic devices.
Referring to FIG. 1 showing a functional block diagram of a conventional liquid crystal display 10, the liquid crystal display 10 includes a liquid crystal panel 12, a gate driver 14, and a source driver 16. The liquid crystal panel 12 includes a plurality of pixels, each pixel having three pixel units 20 indicating three primary colors, red, green, and blue. For example, the liquid crystal display 12 with 1024 by 768 pixels contains 1024×768×3 pixel units 20. The gate driver 14 periodically outputs a scanning signal to turn on each transistor 22 of the pixel units 20 row by row, meanwhile, each pixel units 20 is charged to a corresponding voltage based on a data signal from the source driver 16, to show various gray levels. After a row of pixel units is finished to be charged, the gate driver 14 stops outputting the scanning signal to this row, and then outputs the scanning signal to turn on the transistors 22 of the pixel units of the next row. Sequentially, until all pixel units 20 of the liquid crystal panel 12 finish charging, and the gate driver 14 outputs the scanning signal to the first row again and repeats the above-mentioned mechanism.
As to the conventional liquid crystal display, the gate driver 14 functions as a shift register. In other words, the gate driver 16 outputs a scanning signal to the liquid crystal display 12 at a fixed interval. For instance, a liquid crystal display 12 with 1024×768 pixels and its operating frequency with 60 Hz is provided, the display interval of each frame is about 16.67 ms (i.e., 1/60 second), such that an interval between two scanning signals applied on two row adjacent lines is about 21.7 μs (i.e., 16.67 ms/768). The pixel units 20 are charged and discharged by data voltage from the source driver 16 to show corresponding gray levels in the time period of 21.7 μs accordingly.
Unfortunately, regarding the gate driver 14 manufactured with an amorphous silicon (a-Si) technology, the liquid crystal display 12 may display unevenly due to a voltage stress phenomenon which causes a discrepancy of threshold voltages of any two transistors. Referring to FIG. 2 illustrating a timing diagram of a conventional shift register, as disclosed in U.S. Pat. No. 7,310,402, output OUT-N of the shift register fails to reach high voltage level rapidly, and thus the transistor of the pixel is incapable of being turned on in time, such that a charge time period of the pixel is limited. Therefore, it is possible that insufficient charge time period for the pixel may degrade display quality.
A shift register disclosed in U.S. Pat. No. 5,222,082 includes a plurality of register units electrically coupled in cascade. Each register unit is used for delaying an input signal and outputting an output signal based on clock signals. Then the next register unit delays the output signal of the previous register unit, and thus outputs an output signal. However, voltage applied at gates of transistors of each register unit may keep a high voltage level for a long while until next scanning period for the next frame. In this way, the gate voltage applied to the transistors results in a voltage shift. When the transistor is under a positive voltage stress, the longer the stress time is, the greater the shift range of threshold voltage of the transistor is. However, the stress time of the positive voltage stress may degrade operation efficiency and reduce the life of the transistor, even shorten the life of the whole shift register.
In order to reduce the damage of the transistor caused by the voltage stress phenomenon that the high voltage level is applied at the gate of the transistor for a long while, a resolution is to shorten a time period over which the high voltage level is applied at the gate of the transistor. A shift register disclosed in U.S. Pat. No. 5,517,542, the delay output of the Nth stage register unit is controlled by the output OUTn+2 of the (N+2)th stage register unit. A shift register disclosed in U.S. Pat. No. 6,845,140, the delay output of the Nth stage register unit SRN is controlled by the output GOUTN+1 of the (N+1)th stage register unit SRN+1. In other words, a transition of the gate voltage of the current transistor from the high voltage level to the low voltage level is determined by the output signal of the next stage or the next two stage register unit of such two shift registers, so that the voltage applied on the gate of the transistor does not keep the high voltage level for a long time, thereby reducing voltage stress phenomenon for the transistor. Because such two register units utilize the output signal of next stage or next two stage register units as a control signal to adjust the transition of the gate voltage of the transistor of the current register unit, the signal interference inevitably occurs.